1. Field of the Invention
The present invention relates to a semiconductor integrated circuit including a digital circuit which includes a logic circuit and a register circuit, the setup time and the hold time of which can be easily measured.
2. Description of Related Art
As seen in, for example, a system LSI, a conventional clock-synchronized digital circuit is configured in such a manner as described below. That is, at least one logic circuit is disposed in a stage following an input buffer connected to an input terminal. The output of that one logic circuit is temporarily retained by a register circuit configured with a flip-flop. Then, the logic output is further supplied to a subsequent register circuit through a subsequent logic circuit.
In a circuit having such a configuration as described above, data is loaded into a register circuit in synchronization with a rising or falling edge of a clock signal. This means that the register circuit is controlled from the outside by a clock signal input to the clock terminal thereof.
In the register circuit, the time required to load data is not zero. Therefore, the data must be fixed (stabilized) during certain periods of time before and after data loading. Part of the period before data loading (prior to the rising edge of a clock signal) is referred to as a setup time “t su”, whereas part of the period after data loading (subsequent to the falling edge of the clock signal) is referred to as a hold time “t hold”. The setup time “t su” is a minimum time during which input data must be stabilized before a valid edge of the clock signal is encountered in a register circuit or a latch circuit, in order to correctly read the input data. Likewise, the hold time “t hold” is a minimum time during which input data must be stabilized after a valid edge of the clock signal is encountered in the register circuit or the latch circuit, in order to correctly read the input data. This means that data must be fixed at least during a period of “t su+t hold” when data is loaded. If this requirement is ignored, the operation of a flip-flop is not guaranteed. Consequently, when data is input to the register circuit, it is necessary to verify (observe) the timing of data input/output with respect to a clock edge. An LSI tester is commonly used in order to verify the timing of data input/output with respect to the clock edge.
However, a conventional digital circuit is configured so that a plurality of complex logic circuits exists in a path from an input buffer to a first-stage register circuit. Since the first-stage register circuit configured to load logic outputs is located in a stage following the logic circuits, a wiring delay arises in each logic output due to the complex logic circuits in a preceding stage when data is loaded into the first-stage register circuit. It is therefore difficult to synchronize the timing of data with a rising or falling edge of the clock signal. It is also difficult to dispose means for directly observing the output of the first-stage register circuit located in a subsequent stage since the complex logic circuits exist in the preceding stage.
In a semiconductor integrated circuit of the related art, a switch circuit 3 is provided in the output section of a register circuit 2-1 provided in a stage following the input circuit 1-1 of a pin under measurement Di, as shown in, for example, Japanese Patent Application Laid-Open Publication No. 2000-258499. One contact of the switch circuit 3 is connected to the output of the register circuit 2-1 and the other contact is connected to a pin for judgment Do. The register circuits 2-1 and 2-2 are controlled by a clock signal C. A test mode signal TST is input when a test of the pin under measurement Di is conducted. Consequently, the switch circuit 3 goes to an on-state, thereby connecting the output of the register circuit 2-1 and the pin for judgment Do to each other through the switch circuit 3. Thus, the output of the register circuit 2-1 is obtained at the pin for judgment Do.
However, Japanese Patent Application Laid-Open Publication No. 2000-258499 specifically describes an input buffer and a register circuit connected to an address pin and an I/O pin used in a memory product. Thus, the invention described in Japanese Patent Application Laid-Open Publication No. 2000-258499 is not intended to observe the setup time “t su” and the hole time “t hold” of register circuits used in a plural number in a digital circuit configured with logic circuits and register circuits like the above-described system LSI.